1. Field of the Invention
The present invention relates generally to integrated circuit chip package technology and, more particularly, to a semiconductor package wherein the conductive wires used to facilitate the electrical connection of a semiconductor die of the package to a leadframe or substrate thereof are exposed in a package body of the package to allow a mating semiconductor device or package to be mounted and electrically connected thereto.
2. Description of the Related Art
Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body.
The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe extend externally from the package body or are partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die attach pad or die pad of the leadframe also remains exposed within the package body. In other semiconductor packages, the metal leadframe is substituted with a laminate substrate to which the semiconductor die is mounted and which includes pads or terminals for mimicking the functionality of the leads and establishing electrical communication with another device.
Once the semiconductor dies have been produced and encapsulated in the semiconductor packages described above, they may be used in a wide variety of electronic devices. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically includes a printed circuit board on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic devices are typically manufactured in reduced sizes and at reduced costs, which results in increased consumer demand. Accordingly, not only are semiconductor dies highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
Even though semiconductor packages have been miniaturized, space on a printed circuit board remains limited and precious. Thus, there is a need to find a semiconductor package design to maximize the number of semiconductor packages that may be integrated into an electronic device, yet minimize the space needed to accommodate these semiconductor packages. One method to minimize space needed to accommodate the semiconductor packages is to stack the semiconductor packages on top of each other, or to stack individual semiconductor devices or other devices within the package body of the semiconductor package. In general, three-dimensional stacked packaging is a field of system-in-package (SIP) technology where semiconductor die or package stacking is used to provide a higher volume density in the thickness direction for the stacked packaging. Such three-dimensional stacked packaging enables integration of a variety of devices, including flash memories, SRAM's, DRAM's, basebands, mixed signal devices, analog devices and logic devices, and is thus essential in reducing the size, weight and price of portable electronic/communication devices. A typical three-dimensional package stack is a stack of semiconductor packages, each of which includes electrode terminals on upper and lower surfaces thereof, in the direction of thickness. In one exemplary configuration, a substrate extends a predetermined length outside an encapsulant or package body, with solder balls being formed on upper and lower surfaces of the substrate, and the overlying semiconductor package being electrically interconnected to the underlying semiconductor package by the solder balls. In some cases, an interposer having interconnection patterns is interposed between the overlying and underlying semiconductor packages to form a stack of such semiconductor packages.
However, this and other existing stacking solutions possess certain deficiencies which detract from their overall utility. In this regard, the use of the extended substrate or the additional interposer often results in electrical paths of increased length in the package stack, thus deteriorating the electrical performance of the semiconductor packages therein. Additionally, when attempting to integrate a large number of devices such as memory chips into a vertical stack within a single semiconductor package, test yield loss typically becomes higher as more such devices are assembled in a single package. As a result, it becomes desirable to use multiple packages which each contain a subset of the memory chips or devices to be integrated vertically. Further, many semiconductor package stacking approaches result in excessive increases in the area and/or thickness or the package stack, and thus are not suitable for portable electronic/communication devices that are becoming gradually lighter in weight and smaller in size and thickness. The present invention addresses these and other deficiencies, and provides a three-dimensional packaging solution wherein the individual semiconductor package(s) of the stack is/are uniquely structured to have a reduced profile, thus effectively minimizing the overall stack height of a package stack assembled to include the same. These, as well as other features and attributes of the present invention will be discussed in more detail below.